As the focus of applied research in topological insulators (TI) evolves, the need to synthesize large-area TI films for practical device applications takes center stage. However, constructing scalable and adaptable processes for high-quality TI compounds remains a challenge. To this end, a versatile van der Waals epitaxy (vdWE) process for custom-feature bismuth telluro-sulfide TI growth and fabrication is presented, achieved through selective-area fluorination and modification of surface free-energy on mica. The TI features grow epitaxially in large single-crystal trigonal domains, exhibiting armchair or zigzag crystalline edges highly oriented with the underlying mica lattice and only two preferred domain orientations mirrored at 180°. As-grown feature thickness dependence on lateral dimensions and denuded zones at boundaries are observed, as explained by a semiempirical two-species surface migration model with robust estimates of growth parameters and elucidating the role of selective-area surface modification. Topological surface states contribute up to 60% of device conductance at room temperature, indicating excellent electronic quality. High-yield microfabrication and the adaptable vdWE growth mechanism with readily alterable precursor and substrate combinations lend the process versatility to realize crystalline TI synthesis in arbitrary shapes and arrays suitable for facile integration with processes ranging from rapid prototyping to scalable manufacturing.Keywords: bismuth telluride sulfide; lithographic patterned growth; multispecies surface migration; selective-area van der Waals epitaxy; surface fluorination; ternary topological insulators; two-dimensional layered chalcogenides;

We report the fabrication and device characteristics of exfoliated, few-layer, dual-gated ReS2 field effect transistors (FETs). The ReS2 FETs display n-type behavior with a room temperature Ion/Ioff of 105. Many devices were studied with a maximum intrinsic mobility of 12 cm2·V–1·s–1 at room temperature and 26 cm2·V–1·s–1 at 77 K. The Cr/Au-ReS2 contact resistance determined using the transfer length method is gate-bias dependent and ranges from 175 kΩ·μm to 5 kΩ·μm, and shows an exponential dependence on back-gate voltage indicating Schottky barriers at the source and drain contacts. Dual-gated ReS2 FETs demonstrate current saturation, voltage gain, and a subthreshold swing of 148 mV/decade.Keywords: gain; mobility; rhenium disulfide; saturation; TMD; transistor;

We fabricate and characterize a set of dual-gated graphene field effect transistors using a novel physical vapor deposition technique in which titanium is evaporated onto the graphene channel in 10 Å cycles and oxidized in ambient to form a top-gate dielectric. A combination of X-ray photoemission spectroscopy, ellipsometry, and transmission electron microscopy suggests that the titanium is oxidizing in situ to titanium dioxide. Electrical characterization of our devices yields a dielectric constant of κ = 6.9 with final mobilities above 5500 cm2/(V s). Low temperature analysis of the gate-leakage current in the devices gives a potential barrier of 0.78 eV in the conduction band and a trap depth of 45 meV below the conduction band.Keywords: dielectric; gate leakage; graphene; seed layer; titanium oxide; transistor;

Mechanically flexible integrated circuits (ICs) have gained increasing attention in recent years with emerging markets in portable electronics. Although a number of thin-film-transistor (TFT) IC solutions have been reported, challenges still remain for the fabrication of inexpensive, high-performance flexible devices. We report a simple and straightforward solution: mechanically exfoliating a thin Si film containing ICs. Transistors and circuits can be prefabricated on bulk silicon wafer with the conventional complementary metal–oxide–semiconductor (CMOS) process flow without additional temperature or process limitations. The short channel MOSFETs exhibit similar electrical performance before and after exfoliation. This exfoliation process also provides a fast and economical approach to producing thinned silicon wafers, which is a key enabler for three-dimensional (3D) silicon integration based on Through Silicon Vias (TSVs).

As a result of recent trends in processor speed and core temperature, III–V semiconductors have become a tempting replacement for Si in semiconductor logic. However, as device geometries shrink, the advantages of such a switch are put into question. In this paper we present a computational survey of III–V materials in a tri-gate nanowire MOSFET geometry as compared with Si to determine an optimal material choice for this geometry using a 3D semi-classical Monte Carlo simulation tool. We show that InSb and InAs show promise as future materials for next generation switching devices.Research highlights► 3D Semiclassical Monte Carlo simulation of III–V and Si tri-gate nanowire FETs. ► Schrodinger correction with Poisson solver and non-parabolic band approximation. ► Carrier velocity as opposed to quantum/dos capacitances vary Ids between materials. ► InAs and InSb show superior performance.

We demonstrate the synthesis of large-area graphene on Co, a complementary metal-oxide-semiconductor (CMOS)-compatible metal, using acetylene (C2H2) as a precursor in a chemical vapor deposition (CVD)-based method. Cobalt films were deposited on SiO2/Si, and the influence of Co film thickness on monolayer graphene growth was studied, based on the solubility of C in Co. The surface area coverage of monolayer graphene was observed to increase with decreasing Co film thickness. A thorough Raman spectroscopic analysis reveals that graphene films, grown on an optimized Co film thickness, are principally composed of monolayer graphene. Transport properties of monolayer graphene films were investigated by fabrication of back-gated graphene field-effect transistors (GFETs), which exhibited high hole and electron mobility of ∼1600 cm2/V s and ∼1000 cm2/V s, respectively, and a low trap density of ∼1.2 × 1011 cm–2.Keywords: acetylene; cobalt; graphene; mobility; transistor

We report on the gigahertz radio frequency (RF) performance of chemical vapor deposited (CVD) monolayer MoS2 field-effect transistors (FETs). Initial DC characterizations of fabricated MoS2 FETs yielded current densities exceeding 200 μA/μm and maximum transconductance of 38 μS/μm. A contact resistance corrected low-field mobility of 55 cm2/(V s) was achieved. Radio frequency FETs were fabricated in the ground–signal–ground (GSG) layout, and standard de-embedding techniques were applied. Operating at the peak transconductance, we obtain short-circuit current-gain intrinsic cutoff frequency, fT, of 6.7 GHz and maximum intrinsic oscillation frequency, fmax, of 5.3 GHz for a device with a gate length of 250 nm. The MoS2 device afforded an extrinsic voltage gain Av of 6 dB at 100 MHz with voltage amplification until 3 GHz. With the as-measured frequency performance of CVD MoS2, we provide the first demonstration of a common-source (CS) amplifier with voltage gain of 14 dB and an active frequency mixer with conversion gain of −15 dB. Our results of gigahertz frequency performance as well as analog circuit operation show that large area CVD MoS2 may be suitable for industrial-scale electronic applications.