•The paper studies the impact of post-metal annealing on reliability of 65 nm flash cell.•The experiments show that the erasing speed is obviously degraded using PMA treatment.•The higher density of interface and bulk oxide traps can be found in PMA flash cell.•The water diffuse during PMA process is considered to main cause of traps generation.•Remove PMA treatment is the best way to suppress the water diffusion effect in our work.This paper investigates the impact of post-metallization annealing (PMA) in pure nitrogen ambient on the reliability of 65 nm NOR-type floating-gate flash memory devices. The experimental results show that, with PMA process, the cycling performance of flash cells, especially for the erasing speed is obviously degraded compared to that without PMA. It is found that the bulk oxide traps and tunnel oxide/Si interface traps are significantly increased with PMA treatment. The water/moisture residues left in the interlayer dielectric layers diffuse to tunnel oxide during PMA process is considered to be responsible for these traps generation, which further enhances the degradation of erase performance. Skipping PMA treatment is proposed to suppress the water diffusion effect on erase performance degradation of flash cells.

•CHEI-P and PASHEI programs are compared in 90 nm SONOS devices.•CHEI-P program exhibits the superior reliability.•The accumulation charges in the nitride layer are investigated.•CHEI-P program exhibits the good characteristics at 4-bit 4-level states.In order to obtain a reliable multi-bit/level operation for nano-scaled polycrystalline silicon-oxide-nitride-oxide-silicon (SONOS) memory, two different localized charge-injection programming methods, the channel hot electron injection with a positive substrate bias (CHEI-P) and pulse agitated substrate hot electron injection (PASHEI), are operated in 90 nm SONOS cells. It is found that the cells programmed by CHEI-P have the better endurance property than by PASHEI. The better endurance is due to the less accumulation of charges in the nitride layer, evidenced by surface potential profiling technique. CHEI-P program further exhibits the superior endurance and retention properties after 104 program/erase cycles in 4-bit/4-level operations. These results illustrate that CHEI-P program is a promising candidate for multi-bit/levels nano-sized SONOS memory.

As the cell size scales down to 90 nm node, the mismatch of spatial charge distribution dramatically aggravates the reliability degradation of localized trapping polysilicon–oxide–nitride–oxide–silicon (SONOS) memory, especially in multilevel cell and multi-bits/cell applications. The secondary electron injection (SEI) is thought to be the root cause of mismatch between injected electrons and holes. A channel hot electron injection (CHEI) programming technique with a positive substrate bias was proposed to effectively suppress SEI effect. In this work, a similar programming method is used in 90 nm localized trapping SONOS devices for multilevel cell and multi-bits/cell storage. In contrast to the reported positive substrate biased CHEI programming, we apply a source bias of 1 V instead of 0 V to prevent the forward-biased source/substrate junction so that the programming power consumption is greatly reduced. It is experimentally found that a sharp electron profile near the junction edge is obtained. A better matched profile of the injected electrons and holes substantially improves the cycling endurance and data retention of 4-bits/cell memory at the four-level states.

The impact of shallow trench isolation (STI) on non-volatile memories becomes much more severe with the CMOS technology scaling down to sub-90 nm. In this work, the impact of STI on a polysilicon–oxide–nitride–oxide–silicon (SONOS) type memory has been investigated based on the experiments and TCAD simulation analysis. It has been found edge cells adjacent to STI have the lower channel-hot-electron (CHE) injection programming efficiency than center cells. In addition, edge cells exhibit different initial threshold voltage (Vt) distribution compared with center cells. STI impact is thought to be the main reason for these problems. To reduce the impact of STI, an additional boron implantation in STI BL contacts region is developed as a new solution. As a result, the performance differences between edge and center cells have been substantially minimized.